1. Field of the Invention
The invention relates to digital computers, particularly with respect to computers configured to operate in an overlapped fashion.
2. Description of the Prior Art
In the prior art computers have been operated in overlapped fashion to enhance performance with respect to throughput. This technique, known as "pipe lining," suffers degradation in performance when conditional branches and jumps are encountered. Under these circumstances it has been necessary to waste computer cycles since in the overlap mode the next instruction has already been fetched when the conditional branch is encountered. Although pipe lining has been applied at the macro program level, it has heretofore not been utilized at the micro instruction level in a micro programmed computer since the degradation in speed suffered because of the numerous conditional branches and jumps necessitated at the micro level substantially destroys the enhancement in performance that pipe lining would be expected to provide. Specifically, when utilizing overlap, conditional branching can result in wasted cycles because the instruction fetch is overlapped with the instruction execution. The executed instruction may compute a condition indicating that a branch should be taken but the next instruction has already been fetched. Computer cycles are also wasted in prior art arrangements because of the necessity to wait for computed results to be stored away prior to proceeding with the next instruction.
It is the primary object of the present invention to provide a highly overlapped computer architecture without the time penalty degradation encountered in the prior art due to conditional branches and jumps.